library IEEE;
use IEEE.std_logic_1164.ALL;

entity S_R is 
	port (
		set,reset: IN std_logic;
		Q,QN,S_out,R_out: OUT std_logic
	);
	end S_R;
	
	architecture arch of S_R is
	signal Qs,Qns,Ss,Rs: std_logic;
	
	begin
	Qns <= not(Set or Qs);
	Qs <= not(Reset or Qns);
	QN <= Qns;
	Q <= Qs;
	Ss <= set;
	Rs <= reset;
	S_out <= Ss;
	R_out <= Rs;	
	end arch;